Adder or Nether

Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs

An exclusive-OR transform of input variables significantly reduces the size of the PLA implementation for adder and comparator circuits. For n bit adder circuits, the size of PLA for transformed functions is O(n2). In comparison, when the complete truth-table of an adder is minimized, the PLA size will be O(2n+2). Similarly, for an n bit comparator, the size of the PLA is reduced from O(2n+1) t...

Military Architecture in the Nether- Lands and Her Former Colonies

Low Power Optimization Of Full Adder, 4-Bit Adder And 4-Bit BCD Adder

Micro-electronic devices are playing a very prominent role in electronic equipments which are used in daily life. For electronic equipment battery life is important. So, in order to reduce the power consumption we implement a Sleepy technique to the electronic circuits. Sleepy technique is also called as power gating technique. In the power gating structure, a circuit operates in two different ...

Performance Analysis of Flagged BCD Adder and Pipelined BCD Adder

BCD Adder is the fundamental adder we learn in logic design and any basic electronics lab. Conventional BCD Adder what we generally know is not feasible for higher bits as they require more area and as they have more propagation delay for higher bit extension. For higher level application BCD design we require more efficient basic BCD block. So in this paper we proposed 2 types of BCD adders na...

Time-precision flexible adder

A new conception of flexible calculation that allows us to adjust a sum depending on the available time computation is presented. More specifically, the objective is to obtain a calculation model that makes the processing time/precision more flexible. The addition method is based on carry-select scheme adder and the proposed design uses precalculated data stored in look-up tables, which provide...